C.Bebek
                                                              15-Sep-1989
							      M. Bishai
							      15-feb-1996  
							      (increased record
								length)
							      14-Nov-1996
							      (added SV info)

              C3L crate constants database file structure
 			for CLEO II and II.5
 
 
The crate constant loader program C3L uses a direct access file
LNS309::U:[PASS1.CCON]C3L.FIL.  Each record is 8196 16-bit words long
(CLEO II records were 4100 16-bit words long) and there are 127 records 
in the file, 1 through 127.  The records are usually  addressed by crate 
number.  The general structure of each record is:
 
              HEADER(1) to HEADER(4)
              DATA(1) to DATA(4096) CLEO II
	      DATA(1) to DATA(8192) CLEO II.5 (SV)
 
For records that contain no crate data, the HEADER format is:
 
              HEADER(1)         record number
              HEADER(2)         device name:  XX
              HEADER(3)         zero
              HEADER(4)         zero
 
 
For analog crate controllers, the HEADER format is:
 
              HEADER(1)         record number:  crate number
              HEADER(2)         device name:  PT,VD,DR,TF,MU
              HEADER(3)         number of DATA items containing data - 4 times
                                the number of detector elements.
              HEADER(4)         starting address in crate controller memory to
                                store the constants.  For TF this is 4 times
                                the number of detector elements and for all
                                others this is 3 times the number of detector
                                elements.
 
For the PT, VD, and DR the DATA array contains sets of four word entries for
each wire/cathode as follows:
 
              1      High time cut
              2      Low time cut
              3      High charge cut
              4      CELLID
 
 
For TF, the DATA array contains sets of four-word entries for each phototube
as follows:
 
              1      Time 1 high cut
              2      Time 2 high cut
              3      Charge cut
              4      CELLID
 
 
For MU, the DATA array contains sets of four-word entries for each wire/strip
pair as follows:
 
              1      Charge 1 low cut
              2      Charge 2 low cut
              3      Zero
              4      CELLID
 
 
The CC SPARXL board requires two theshold memories to be loaded.  The
controller is crate "100.  Since more data is required than can fit into the
standard 4096 word record, this crate uses records "100 and "102 for the seed
thresholds and records "103, and "104 for the skim thresholds.  The HEADER for
CC records is as follows:
 
		
              HEADER(1)       record number: "100,"102,"103, or "104
              HEADER(2)       device name:  CC
              HEADER(3)       number of DATA items used - 4096 in all cases.
              HEADER(4)       starting address in threshold RAM - 0 for "100
                              and "103;  4096 for "102 and "104.
 
 
The DATA array for these records is as follows (remember that the RAM entries
must be in SPARXL order with the index 1 being in RAM location 1):
 
              "100            seed RAM(0) to RAM(4095)
              "102            seed RAM(4096) to RAM(8191)
              "103            skim RAM(0) to RAM(4095)
              "104            skim RAM(4096) to RAM(8191)
 
 
Each CC mixer/shaper card requires two 64-bit shift registers to be loaded,
one for diode summation control and the other for crystal gain control.  Since
the required data is greater that 4096 words, record "101 is used for the
summer switches and record "105 is used for the gain switches.  There are 504
total mixer/shaper cards distributed in 24 chasses.  Chasses 1 to 16 are for
the CB and contain 24 cards each.  Chasses 17 to 24 are for the CE and contain
15 cards each.  The HEADER words are as follows:
 
              HEADER(1)       record number: "101 or "105
              HEADER(2)       device name:  MS
              HEADER(3)       5*504
              HEADER(4)       zero
 
 
The DATA array contains 504 5-word entries.  Let X1 through X16 represent the
four-bit nibble to control the sum or gain for each crystal on a mixer/shaper
board.  Each entry is then of the form:
 
          1   ishft(CHASSIS,8) .or. CARD
          2   ishft(X4,12) .or. ishft(X3,8) .or. ishft(X2,4) .or. X1
          3   ishft(X8,12) .or. ishft(X7,8) .or. ishft(X6,4) .or. X5
          4   ishft(X12,12) .or. ishft(X11,8) .or. ishft(X10,4) .or. X9
          5   ishft(X16,12) .or. ishft(X15,8) .or. ishft(X14,4) .or. X13
 
Note that since each 64-bit shift-register datum is preceded by a card
address, the order of the cards in the DATA array can be arbitrary.

For SV the header format is as follows:
  
              HEADER(1)         record number:  crate number "128 to "144
              HEADER(2)         device name:  SV
              HEADER(3)         number of DATA items containing channel data 
                                = 4 times the number of detector elements.
              HEADER(4)         starting address in crate controller memory to
                                store the constants.  For SV this is 4 times
                                the number of detector elements.

For the SV the DATA array contains sets of four word entries for each channel 
as follows:

              1      Threshold
              2      Live/Dead
              3      Pedestal
              4      LogAddress

After the channel data in the same record there are CAMEX specific constants 
for 26 CAMEX chips in sets of four word entries:

              1      Cluster threshold (ThrSum)
              2      Treshold for CMN calculation (ThrCMN)
              3      Send all channels flag (SendALL)
              4      Number of "good" channels on this chip (Ngood)

followed by an additional set of 26 CAMEX constants in sets of four word 
entries:

              1      Logical address for CMN value (CMN)
              2      Logical address for CMN slope (SLP)
              3      Threshold for maximum pulse height (SendALL)
              4      This word not used always = 0